1. Field of the Invention
The present invention relates to the field of digital circuits. In particular, the present invention relates to the verification of digital circuits.
2. Brief Description of the Related Art
Digital or logic circuits are implemented in almost any electronic device available today and offer the possibility of integrating an increasing number of functions and features into devices without raising production costs considerably. However, with the increasing number of features and functions, the number of circuit elements and thereby the complexity of the digital or logic circuits has increased. Consequently, the effort undertaken to design the digital or logic circuits has enormously increased.
In usual design procedures an engineer or a team of engineers develops a design of the logic circuit or an assembly of the logic circuits that implements the desired functions. In order to represent or describe a design a number of description modes and methods have been developed describing a logic circuit at different levels. These description modes and methods include, for example, RTL or net list description.
Once the design for the logic circuit has been developed and described according to the requirements of the desired application, a chip layout of the logic circuit has to be designed before the chip production process is started. It has become evident that mistakes or unforeseen circuitry may cause malfunctions in the chip which results in high costs for the correction of the design once the chip production process has started. Therefore, verification methods have been introduced in order to verify that the design of the chip layout fulfils all the requirements of the desired logic circuit. These verification methods may be applied before the production process or even during the design steps in order to find any faults in the design of the chip layout as soon as possible.
The verification methods analyse the function and/or the layout of the design of the chip layout in order to simulate the function of the chip. Different types of the verification methods, i.e. timing verification or functional verification methods, are currently known in the art.
The aim of static timing analysis is to verify that a logic circuit, in particular a digital circuit, satisfies its timing constraints, i.e. that the logic circuit will function correctly when run at an intended speed.
It is state of the art in static timing analysis to check for potential setup (and hold) time violations by computing longest paths (with respect to gate and wire delays) through the logic circuit. It is well known that this check may be too conservative, because the check may find critical paths which cannot be activated while the chip is operating. This is due to the fact that static timing analysis performs a pure topological analysis of the logic circuit and does not take the functionality of the logic circuit into account. It is state of the art in static timing analysis to circumvent this problem by specifying so called timing exceptions. Timing exceptions are typically used for specifying paths to be false paths or to be multi-cycle paths. The timing exceptions are typically provided by the user of static timing analysis tools. The timing exceptions have the effect that those timing violations, which are specified to be exceptional, are simply ignored by the static timing analysis tool. It is evident that this procedure is error-prone. For example, static timing analysis may ignore relevant timing violations if the timing violation has been wrongly specified to be a timing exception, termed invalid timing exception which can lead to operational malfunction of the logic circuit. Timing violations that are correctly specified as timing exceptions are termed valid timing exception.
Therefore, there is a need for an automated system which allows to check whether a set of given timing exceptions or timing violations is valid or to find a set of valid timing exceptions that is fast and reliable even with a large logic circuits and large numbers of timing violations.
There are different published methods and available software tools which claim to solve this task at least partially. However, all of them suffer from different drawbacks. A large variety attacks the special case of false path exceptions. Most of them are trying to find a way to characterize a single path as false or true. It is well known, that these methods are either faulty, or too weak, or they need exact gate delay times. Only a few seem to be aware of the problem that a set of false path exceptions has to be analyzed as an entirety to decide whether it is valid or not.
U.S. Pat. No. 5,638,290 describes a method for removing critical false paths during logic optimization based on a redundancy removal algorithm using essentially thee steps: starting a timing verification, searching for critical paths, extracting critical cones. This method has to be iteratively repeated for as long as a critical path is false.
However, there is no method available to analyze different kinds of timing exceptions, e.g. multi cycle paths and false paths simultaneously.
Further, there is a need for an automated system and a method for checking exceptions or violations, in particular timing exceptions, in a logic circuit that is fast, reliable and applicable to complex logic circuits.
There is also a need for a method and a system for checking exceptions in a logic circuit that can be implemented in standard verification procedures.
It is therefore an object of the present invention to provide a system for verifying exceptions that allows the automated determination whether a set of exceptions is of influence for the proper function of the chip or not.